1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same, and in particular, to a semiconductor memory device allowing electrical writing and erasing of information as well as a method of manufacturing the same.
2. Description of the Background Art
As one of nonvolatile semiconductor memory devices, there has been known an EEPROM (Electrically Erasable and Programmable Read Only Memory) in which data can be freely programmed and which allows electrical writing and erasing of information. Although the EEPROM has an advantage that both writing and erasing can be executed electrically, it disadvantageously requires two transistors for each memory cell, and therefore integration to a higher degree is difficult. For this reason, there has been proposed a flash EEPROM including memory cells, each of which is formed of one transistor, and allowing electrical entire chip erasing of written electric information charges, for example, in U.S. Pat. No. 4,868,619.
FIG. 53 is a block diagram showing a general structure of a flash EEPROM in the prior art. Referring to FIG. 53, the flash EEPROM includes a memory cell matrix 100, an X-address decoder 200, a Y-gate sense amplifier 300, a Y-address decoder 400, an address buffer 500, an I/O (input/output) buffer 600 and a control logic 700.
The memory cell matrix 100 includes a plurality of memory cells arranged in rows and columns. The X-address decoder 200 and Y-gate sense amplifier 300 are connected to the memory cell matrix 100 for selecting the rows and columns thereof. The Y-address decoder 400 is connected to the Y-gate sense amplifier 300 for applying selection information of column thereto. The address buffer 500 is connected to the X-address decoder 200 and Y-address decoder 400, and temporarily stores the address information.
The Y-gate sense amplifier 300 is connected to the I/O buffer 600 for temporarily storing I/O data. The control logic 700 is connected to the address buffer 500 and I/O buffer 600 for controlling an operation of the flash EEPROM. The control logic 700 carries out the control based on a chip enable signal (/CE), an output enable signal (/OE) and a program signal (/PGM).
FIG. 54 is an equivalent circuit diagram showing a schematic structure of the memory cell matrix 100 shown in FIG. 53. Referring to FIG. 54, the memory cell matrix 100 includes a plurality of word lines WL1, WL2, . . . WL1 extending in a row direction and a plurality of bit lines BL1, BL2, . . . , BL1 extending in a column direction and perpendicularly crossing the word lines. At crossings of the word lines and bit lines, there are disposed memory transistors Q11, Q12, . . . Q11 each having a floating gate electrode, respectively. Each memory transistor has a drain connected to the corresponding bit line, and a control gate electrode connected to the corresponding word line. A source of each memory transistor is connected to corresponding one of the source lines SL1, SL2 . . . , SL1, which are connected to source lines S1 and S2 disposed at opposite sides.
FIG. 55 is a schematic plan showing a flash EEPROM of a stack gate type in the prior art. FIG. 56 is a cross section taken along line Axe2x80x94A in FIG. 55. Referring to FIGS. 55 and 56, a structure of the flash EEPROM in the prior art will be described below.
Referring to FIG. 55, control gate electrodes 137 are mutually connected to form word lines extending in a lateral direction (row direction). Bit lines 139 extend perpendicularly to the word lines 137. Each bit line 139 connects drain diffusion regions 132, which are aligned in a longitudinal direction (column direction), to each other. The bit lines 139 are electrically connected to the drain diffusion regions 132 through drain contacts 140. Referring to FIG. 56, the bit line 139 extends over a smooth coat film 141. Referring to FIG. 55 again, source diffusion regions 133 extend along the word lines 137 and are formed in regions surrounded by the word lines 137 and element isolating oxide films 130. Each drain diffusion region 132 is formed in a region surrounded by the word line 137 and element isolating oxide film 130.
Referring to FIG. 56, at a main surface of a P-type silicon substrate 131, there are formed the drain diffusion regions 132 and source diffusion regions 133 at opposite sides of channel regions with predetermined spaces between each other. On the channel regions, there are formed floating gate electrodes 135 with a thin oxide film 134 of about 100xc3x85 in thickness therebetween. The control gate 137 is formed on each floating gate electrode 135 with an interlayer insulating film 136 therebetween for electrically isolating them from each other. The floating gate electrode 135 and control gate electrode 137 are formed of polysilicon layers. A thermal oxide film 138 is formed by thermal oxidation of surfaces of the P-type silicon substrate 131 as well as floating gate electrode 135 and control gate electrode 137 made of polysilicon layers. The floating gate electrode 135 and control gate electrode 137 are covered with the smooth coat film 141 formed of an oxide film or the like.
An operation of the flash EEPROM will be described below with reference to FIG. 56.
In a writing operation, a voltage VD1 of about 6 to 8V is applied to the drain diffusion region 132, and a voltage VG1 of about 10 to 15V is applied to the control gate electrode 137. Thereby, electrons (holes) are accelerated by an electric field near the drain diffusion region 132 and obtain a high energy. The channel hot electrons (holes) which have obtained the high energy are attracted and injected into the floating gate electrode 135 by the electric field which is caused by the voltage VG1 applied to the control gate electrode 137. This is called channel hot electron (hole) injection. The channel hot electrons having the high energy impinge against lattices of silicon to generate electron hole pairs. The electrons (holes) thus generated are attracted and injected into the floating gate electrode 135 by the electric field which is caused by the voltage VG1 applied to the control gate electrode 137. This is called drain avalanche hot carrier injection. If electrons are accumulated in the floating gate electrode 135 by the channel hot electron injection and drain avalanche hot carrier injection, a threshold voltage Vth of the control gate transistor increases. The state where the threshold voltage Vth is higher than a predetermined value is a programmed state and is also referred to as a state of xe2x80x9c0xe2x80x9d.
In an erasing operation, a voltage Vs of about 10 to 12 V is applied to the source diffusion region 133. The control gate electrode 137 is maintained at the ground voltage, and the drain diffusion region 133 is maintained at the floating state. The electric field generated by the voltage Vs applied to the source diffusion region 133 causes the electrons in the floating gate electrode 135 to pass through the thin oxide film 134 by virtue of an F-N (Fowler-Nordheim) tunneling phenomenon. Owing to the removal of electrons in the floating gate electrode 135 in this manner, the threshold voltage Vth of the control gate transistor decreases. This state where the threshold voltage Vth is lower than the predetermined value is an erased state, and is also referred to as a state of xe2x80x9c1xe2x80x9d. Since the sources of transistors are mutually connected as shown in FIG. 55, entire chip erasing of all the memory cells is carried out by this erasing operation.
In reading operation, a voltage VG2 of about 5 V is applied to the control gate electrode 137, and a voltage VD2 of about 1 to 2 V is applied to the drain diffusion region 132. In this operation, the determination of xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d described above is carried out based on whether a current flows through the channel region of the control gate transistor or not, i.e., whether the control gate transistor is in the on-state or off-state. Thereby, information is read.
FIG. 57 is a cross section specifically showing the writing operation of the conventional flash EEPROM. Referring to FIG. 57, the writing operation will be described in greater detail. Both the channel hot electrons (holes) and drain avalanche hot carriers are generated near the drain diffusion region 132. More specifically, the position where the channel hot electrons (holes) are generated is nearer to the source diffusion region 133 than the position where the drain avalanche hot carriers are generated. Therefore, a drain avalanche hot carrier injection region 150 and a channel hot electron (hole) injection region 160 are positioned as shown in FIG. 57. The gate voltage at the time of generation of the channel hot electrons (holes) is larger than the gate voltage at the time of generation of the drain avalanche hot carriers. This is disclosed, for example, in 1982 Symposium on VLSI Technology Digest of Technical Papers, pp. 40-41. FIG. 58 shows correlation between the gate voltage and the gate current corresponding to three different values of the drain voltage VD disclosed in the above reference. As can be seen from FIG. 58, the drain avalanche hot carrier injection is carried out when the gate voltage is low, and the channel hot electron injection is carried out when the gate voltage is high.
FIGS. 59-61 are cross sections showing a process of manufacturing the conventional flash EEPROM shown in FIG. 57. Referring to FIGS. 59-61, the process of manufacturing the conventional flash EEPROM will be described below.
As shown in FIG. 59, a silicon oxide film 134 of about 10 nm in thickness is formed on the surface of the P-type semiconductor substrate 131.
Then, as shown in FIG. 60, a polysilicon film 135, which has a thickness of about 50 to 100 nm and contains impurity introduced thereinto, is formed on the silicon oxide film 134. An interlayer insulating film 136 is formed on the polysilicon film 135. A polysilicon film 137, which has a thickness of about 100 to 200 nm and contains impurity introduced thereinto, is formed on the interlayer insulating film 136. A photoresist 138 is formed at a predetermined region on the polysilicon film 137.
Thereafter, anisotropic etching is effected on the polysilicon film 137, interlayer insulating film 136, polysilicon film 135 and silicon oxide film 134, using the photoresist 138 as a mask. Thereby, the silicon oxide film 134, floating gate electrode 135, interlayer insulating film 136 and control gate electrode 137 are formed as shown in FIG. 61. Thereafter, the photoresist 138 is removed.
Finally, as shown in FIG. 57, N-type impurity is ion-implanted into the P-type semiconductor substrate 131 using the control gate electrode 137 as a mask, whereby the source diffusion region 133 and drain diffusion region 132 are completed.
In the conventional flash EEPROM, the silicon oxide film 134 forms the insulating film under the floating gate electrode 135, so that efficiency of injection of channel hot electrons is low. In the conventional flash EEPROM, electrons injected into the floating gate electrode 135 by the channel hot electron (hole) injection account for 90% of all the electrons injected into the floating gate electrode 135. Therefore, if the efficiency of injection of channel hot electrons decreases, the writing efficiency also decreases remarkably. If the writing efficiency decreases, the speed of writing information also decreases, resulting in difficulty in increasing the speed of the device.
In order to improve the above low efficiency of injection of channel hot electrons, high gate and drain voltages may be applied. However, high gate and drain voltages may deteriorate the breakdown voltage and the reliability of a peripheral circuitry which drives a high voltage when elements are miniaturized to a higher extent.
Further, miniaturization of element causes a disadvantage that injection of drain avalanche hot carriers is liable to generate an interface level. More specifically, the drain avalanche hot carrier has less energy than the channel hot electron. Therefore, the hot carriers injected by the drain avalanche hot carrier injection are liable to stop at the interface between the silicon oxide film 134 and the semiconductor substrate 131 without reaching the floating gate electrode 135. For this reason, the drain avalanche hot carrier injection is liable to cause the interface level. Here, xe2x80x9cinterface levelxe2x80x9d means the energy level at the Si/SiO2 interface region allowing transmission of electric charges to and from the silicon substrate. Generation of such an interface level may cause disadvantages such as variation of the threshold voltage of memory transistors.
In the prior art, as described above, since the efficiency of implantation of channel hot electrons is low, the gate and drain voltages must be high, resulting in disadvantages such as deterioration of the breakdown voltage of the peripheral circuitry driving a high voltage. Further, in accordance with miniaturization of elements, it becomes more likely that the interface level is disadvantageously generated by the drain avalanche hot carrier injection.
An object of the invention is to provide a semiconductor memory device which improves an efficiency of injection of channel hot electrons and suppresses generation of an interface level, which may be caused by drain avalanche hot carrier injection.
Another object of the invention is to provide a semiconductor memory device which suppresses an interface level, which may be caused by drain avalanche hot carrier injection.
Still another object of the invention is to provide a method of manufacturing a semiconductor memory device, which enables easy manufacturing of a semiconductor memory device having a high efficiency of injection of channel hot electrons and capable of suppressing generation of an interface level which may be caused by injection of drain avalanche hot carriers.
According to an aspect of the invention, a semiconductor memory device includes a semiconductor substrate, source and drain regions, a first nitrided oxide film, a second nitrided oxide film, and a gate electrode. The source and drain regions are formed on a main surface of the semiconductor substrate with a predetermined space between each other and are located at opposite sides of a channel region. The first nitrided oxide film is formed at a drain avalanche hot carrier injection region on the main surface of the semiconductor substrate, and contains a first content of hydrogen. The second nitrided oxide film is formed at a channel hot carrier injection region on the main surface of the semiconductor substrate, and contains a second content of hydrogen larger than the first content. The gate electrode is formed on the channel region. Preferably, each of the first and second nitrided oxide film contains nitrogen at 2.5xc3x971020/cm3 or more, the first content is less than 3xc3x971020/cm3, and the second content is 3xc3x971020/cm3 or more.
In the semiconductor memory device according to this aspect of the invention, the first nitrided oxide film containing the first content of hydrogen is formed at the drain avalanche hot carrier injection region, so that the first nitrided oxide film suppresses injection of the drain avalanche hot carriers. At the same time, the second nitrided oxide film containing the second content of hydrogen larger than the first content is formed at the channel hot carrier injection region, so that the second nitrided oxide film improves the efficiency of injection of the channel hot carriers. Consequently, the write efficiency can be improved without increasing the gate and drain voltages in contrast to the prior art.
A semiconductor memory device according to another aspect of the invention includes a semiconductor substrate, source and drain regions, a nitrided oxide film and a gate electrode. The nitrided oxide film is formed at least at a drain avalanche hot carrier injection region on a main surface of the semiconductor substrate, and contains nitrogen of 2.5xc3x971020/cm3 or more and hydrogen of less than 3xc3x971020/cm3.
In this semiconductor substrate, since the nitrided oxide film which contains nitrogen of 2.5xc3x971020/cm3 or more and hydrogen of less than 3xc3x971020/cm3 is formed at the drain avalanche hot carrier injection region, the nitrided oxide film suppresses injection of drain avalanche hot carriers. Thereby, generation of an interface level caused by the injection of drain avalanche hot carriers can be suppressed more effectively even if elements are miniaturized to a higher extent.
A method of manufacturing a semiconductor substrate according to an aspect of the invention includes the step of forming a source region and a drain region which are provided on a main surface of a semiconductor substrate with a predetermined space between each other and are located at opposite sides of a channel region. The method also includes the step of forming a first nitrided oxide film, which contains a first content of hydrogen, at a drain avalanche hot carrier injection region on the main surface of the semiconductor substrate. The method further includes the step of forming a second nitrided oxide film, which contains a second content of hydrogen larger than the first content, at a channel hot carrier injection region on the main surface of the semiconductor substrate. The method also includes the step of forming a gate electrode on the channel region.
In this method of manufacturing the semiconductor memory device, the first nitrided oxide film, which includes the first content of hydrogen, is formed at the drain avalanche hot carrier injection region on the main surface of the semiconductor substrate. The second nitrided oxide film, which contains the second content of hydrogen larger than the first content, is formed at the channel hot carrier injection region on the main surface of the semiconductor substrate. Therefore, the method enables easy manufacturing of the semiconductor memory device which can improve an efficiency of injection of the channel hot carriers while suppressing injection of the drain avalanche hot carriers.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.